This present invention relates generally to manufacturing objects. More particularly, the invention relates to a method and system for measuring and correcting overlay error during photolithographic processing. Merely by way of example, the invention has been applied to the formation and exposure of multiple overlay measurement features. The method and system can be applied to photolithographic processing of CMOS structures as well as other devices, for example, micro-electromechanical systems (MEMS) including sensors, detectors, and displays.
During various semiconductor manufacturing processes, there is a need to control the alignment between various layers present in the semiconductor devices. For example, in the semiconductor manufacturing industry, it is common to fabricate electronic devices by forming and patterning a series of layers (e.g., semiconductors, insulators, metals, and the like) using photolithography processes. As a particular example, the fabrication of MEMS may include the use of photoresist as a sacrificial material supporting suspended structures during an initial stage of the fabrication process. At a later stage of the fabrication process, the sacrificial photoresist is removed to release the suspended structures (e.g., micro-mirrors, accelerometer elements, and the like) so that they are free to move as appropriate to the particular application. Generally, the relative position of the structures both within particular layers and with respect to structures in other layers is an important parameter that impacts the performance of completed electronic devices.
The relative position of structures within an electronic device is generally referred to as overlay and deviations from desired relative positions is generally referred to as overlay error. In some semiconductor processes for encapsulated oxygen-ashable sacrificial materials, overlay error is addressed through the use of conventional photoresist rework. In the photoresist rework process, a first coat of photoresist is applied to the semiconductor substrate and lithographic processing (pre-bake, exposure, post-exposure bake, develop, and the like) is performed to determine the overlay correction values. Flood exposure or a solvent wash is then used to strip the patterned photoresist. A low temperature oxygen plasma process or other cleaning process is then used to remove any residual surface organic residue. A second coat of photoresist is then applied and lithography is performed, taking the overlay error measured during the first portion of the photoresist rework process into account.
The photoresist rework described above presents problems for semiconductor processes including the use of sacrificial materials. For example, the presence of the sacrificial materials at various positions in the structure may limit subsequent temperature processes to particular temperatures and may limit the chemicals to which the structure can be exposed, even when the sacrificial material (e.g., photoresist) is fully encapsulated. Thus, when downstream processes involve overlay correction, which as discussed above, is common when device alignment is an important parameter, stripping of the photoresist can become a challenging and time consuming task. For example, the conventional stripping and rework process typically doubles the number of process steps used to correct for overlay error. Additionally, the conventional process can introduce particles, which adversely impact device yield by increasing the defect density. Thus, there is a need in the art for improved systems and methods for correcting overlay error in photolithographic processes.